The present invention relates to a semiconductor equipped with a conductivity modulating-type MISFET (IGBT) used as an output element for a line driver for serial data transfer, or used as a switching element to drive a multiple power source. More specifically, the present invention relates to a semiconductor equipped with an IGBT in which voltages between a source and a collector are high in terms of blocking voltage in both the forward and reverse directions.
A conventional semiconductor equipped with a conductivity modulating-type MISFET (IGBT) with a high withstand voltage in blocking in both the forward and reverse directions may be exemplified as shown in FIG. 9, in which an n.sup.- -type conductivity modulating layer (103) is formed on a p-type substrate (101) by means of epitaxial growth. In this semiconductor, an n-type embedded layer 102 is formed on the p-type substrate, on which the n.sup.- -type conductivity modulating layer (103) is formed by means of epitaxial growth. A region forming the IGBT is separated from its surroundings with an island-like shape by a p-type isolation (104). On the surface of the conductivity modulation layer (103) in this region, p-type base layers (106) and n.sup.+ -type source layers (107) are formed by double diffusion. A gate oxide film (108) is laminated on these surfaces, over which a gate electrode (109) is disposed to form an MIS section (DMOS) driven by the electrode (109).
First, a p-type deep collector layer (110) and a p.sup.+ -type collector layer (111) are formed on the surface of the conductivity modulating layer (103) at a location opposite to the DMOS section.
Then, an n.sup.+ -type drain wall (105) is formed so as to enclose these collector layers. The drain wall (105) extends from a surface of the conductivity modulating layer (103) to an embedded layer (102). The collector layers (110 and 111) are coupled to a DMOS section (120) or the isolation (104), via the drain wall (105) by means of the conductivity modulating layer (103).
The base layers (106) of the DMOS section (120) and the source layers (107) are connected to a source electrode (121) and the isolation (104) is connected to a source electrode (122), each electrode being applied with a source potential S. The collector layer (111) is provided with a collector electrode (131), to which a collector potential C is applied.
Functions of such an IGBT will be explained by referring to an equivalent circuit as shown in FIG. 11.
First, when a potential G which is a positive bias relative to a source potential S, is applied to the gate electrode 109 the surface of the p-type base layer (106) beneath the gate electrode (109) is inverted, whereby a MOSFET (604) formed in the DMOS section (120) turns on and a potential at the conductivity modulating layer (103) becomes nearly equal to the source potential S. Since the collector potential C is higher than the source potential S and is in forward direction potential, holes are supplied from the collector layers (111 and 110) to which the collector potential C is applied. This turns on a PNP transistor (606) formed of a collector layer (110), a conductivity modulating layer (103) and a base layer (106) and a PNP transistor (606) formed of the collector layer (110), the conductivity modulating layer (103) and the isolation layer (104). As a result, a current flows from the collector electrode (131) to the source electrode (121 or 122) through three paths passing the MOSFET (604), the PNP transistor (603), and the PNP transistor (606).
The IGBT is blocked in the forward direction when the collector potential C is biased positively relative to the source potential S and the gate potential G and is applied to the collector electrode 131, and the source potential S and the gate potential G are the same potential. In this state, a depletion layer (141) extends from a p-n junction of the p-type base layer (106) and the n.sup.- -type conductivity modulating layer (103), and a depletion layer (140) extends from a p-n junction of the p-type isolation layer (104) and the n.sup.- -type conductivity modulating layer (103).
On the other hand, the IGBT is blocked in the reverse direction when the collector potential is biased negatively relative to the source potential and the gate potential and is applied to the collector electrode 131. In this state, a depletion layer (150) extends from a p-n junction of the p-type collector layer and the n.sup.- -type conductivity modulating layer (103).
As described above, a semiconductor equipped with the IGBT shown in FIG. 9 is a device embodying a bidirectional blocking in both the forward and reverse directions.
To construct such an IGBT capable of the bidirectional blocking described above, it is necessary to study prevention of latching up in parasitic thyristors, prevention of punch-through in a blocked condition, prevention of channels due to inversion of the surface of a conductivity modulating layer, and prevention of an avalanche effect at the edges of the collector layers.
In the IGBT shown in FIGS. 9 and 11, if a current amplification h.sub.FE in the PNP transistor (603) is too high, a current flows into a resistance component (601) of the p-type base layer (106), whereby an NPN transistor (602) formed of the n.sup.+ -type source (107), the p-type base layer (106) and the n.sup.- -type conductivity modulating layer (103) turns on. This causes the IGBT to be in a latch-up state, making gate control impossible. To prevent such an occurrence, the current amplification h.sub.FE of the PNP transistor (603) is controlled by the n-type drain wall (105).
Between the p-type base layer (106) and the collector layer (110) and between the p-type isolation layer (104) and the collector layer (110), the n-type deep drain wall (105) is so disposed that it surrounds the collector layer (110). Therefore, the depletion layers (140), (141) and (150) extending over the n.sup.- -type conductivity modulating layer (103) are restricted in spread by the drain wall (105), thus preventing a punch-through that could be attributed to these depletion layers.
The surface of the n.sup.- -type conductivity modulating layer (103) tends to form channels as a result of an inversion due to a very small potential difference. These channels cause short circuits across the p-type base layer (106) and the collector layer (110) as well as across the p-type isolation (104) and the collector layer (110), thus reducing the voltage withstand capability of the IGBT. Formation of the above channels is prevented by disposing the n.sup.+ -type drain wall (105) between the isolation layer (104) and the collector layer (110).
In a reverse direction blocking state where the collector potential C is negatively biased, edges of the collector layer (111) become a high electric field, which leads to an occurrence of avalanche effect, resulting in reduction in the voltage withstand capability of the IGBT. To prevent such a high electric field, the p-type deep or thick collector layer (110) is formed and its edges are formed with a larger curvature.
However, in such an IGBT as that described above, the current amplification h.sub.FE cannot be increased because the n.sup.+ -type drain wall is disposed. Therefore, it is difficult to increase the current carrying capacity of the IGBT. On the other hand if no n-type drain wall is disposed, generation of the latch-up, punch-through and surface channels cannot be prevented, thereby greatly reducing the voltage withstand capability.
To prevent the avalanche effect in the reverse direction blocking state, a deep or thick p-type collector layer is formed. For this reason, the junction of the p-type collector layer and the n.sup.- -type conductivity modulating layer is inclined, and a gradient of the impurity concentration varies continuously.
Therefore, the efficiency of supplying holes from the p-type collector layer to the n.sup.- -type conductivity modulating layer is low, which makes it difficult to improve the conductivity in the conductivity modulating layer. It is also difficult to increase the current-carrying capacity of the IGBT.
Accordingly, an object of the present invention is to obviate the above problems and to provide an IGBT with a large current-carrying capacity while maintaining a voltage withstand capability in a blocking condition by applying to an IGBT preventive means that performs the same functions as a drain wall or a deep collector layer in a blocking condition where a voltage withstand capability is required, and that improves the conducting capability of a conductivity modulating layer in an energized condition.